Transcript
0:00 travel back to Portland to to tear down this phone. We brought one sample back to Singapore for testing. >> What do you mean? You're going to plug it in in Singapore? >> Yeah. And do benchmarks. Yeah. Yeah. This Huawei phone. >> Yeah. It opens up. >> Are you then going to plug a SIM card in it and do some qualitative testing as well? >> Yeah, maybe after that we we might sell it or if the tear down team needs another sample in case anything goes wrong. This is a backup.
0:24 >> You keep the backup tear down in your back pocket. Hello everyone. Welcome back to Semi Analysis Weekly. This is Jordan. I'm here with Howie and Sherry. And in this episode, we're going to be talking through an article that we've just put out called ASML is building a hybrid bonding tool. Big news. It's not been announced yet, but we've got the patent filings. We've made some annotations, and we're going to talk to the experts. So guys, welcome to the show. Excited for this one.
0:52 >> Yeah, thanks for having us on. >> Thanks, Jordan. >> Okay, so take me through it. When did you guys first discover this and what was the initial conversations about when you were getting prepped to write this article? >> Yeah, so the main thing is a tip off from this great guy on Twitter called Little Coffee. Yeah, he made a great series of tweets. I'm not sure how he found the pattern, but it's been there for a while actually this 2025 and shows like specific and a unique strategy in terms of how to integrate the strengths of ASML but apply to hybrid bonding.
1:24 Yeah. So from there we went on and we did a bit more research into the startup super track that is engineering this conveyor system and then we yeah dug in and compared the differences and so it's definitely you know not going to be happening anytime soon it's a several years out but it's at least worth discussing because it's very different to all the current tools out there. Yes. And in fact, we started to well, there was an advanced packaging series that Dylan and other teammates wrote back in 2023 or even earlier. So, we started to focus on this area long time ago and that's why any news in this segment interest us.
2:04 >> Makes sense. So, what's the high level what's the high level difference? Maybe there's some people listening here who don't understand the hybrid bonding description or concept. Can you give the high level intro and then we can talk about the specifics? >> Yeah. So yeah, I would say on a very high level a traditional tool from the likes of Bessie and stuff for a die to wafer system which is what this is going to be is you have a static wafer that is a base a base wafer right for example you have a hybrid bonding you have a top die and a bottom die and so your base wafer will be the target and you'll have a pick and place machine that will take the chiplets for the top die and sort of align them and place them onto the base wafer to make sure that they're all properly aligned. And and so that is the the main tool that we're talking about here. Be before that there's several preparation steps and measurement steps to make sure that everything is aligned and after that there's also other steps of hybrid bonding such as a yielding and processing. So those will not be covered here but the main one is this pick and place tool. And what ASML is doing differently with this pattern is trying to integrate some of the metrology features into a conveyor belt system. So instead of the the dice being taken and placed onto a wafer, now you have the dice going around the carousel around this track that you see here going through the various stations in in each section right for me measurement and for plasma activation right and then finally gone down to the bonding station where the wafer in fact comes up towards the die and meets the die at the carousel and that's where the bonding happens right and this in this specific method right ASML was able to use several of their competencies in terms of measurement mrology as well as wafer stage handling right so they are moving the wafer towards the die rather than the die towards the wafer so that's the main difference here >> sense so you speculate that they could be building a wafer to wafer hybrid bonding tool as well can you maybe describe the difference between diet to wafer versus wafer to wafer >> sure you want to take that >> sure so the difference that the wafer to wafer is basically to bunch your wafers together. Whereas the D to wafer as how we describe is that we'll first have a die and then put the die on the wafer and die to wafer is more challenging compared to wafer to wafer because well it's just it's basically there's higher requirement on the alignment and also right now the mature tools or we are lacking mature tools that can meet both the accuracy and also the throughput that we needs. So that's why I like so based on the patent filings well there are reasons for us to believe that SML is building both but there are more patents about diet wafer that they are building and we believe normally for SML to enter any market they will as they are like their competitive positioning in the lithography so they will aim to be the most advanced and the best so that's why we figure that they could be building both but Now the patent filings suggest that they are moving ahead with the diab wafer.
5:20 >> Okay. So can you guys tell me a little bit about what the existing tools are you mentioned bassie for example it won't be just ASML that's building a hybrid bonding tool. Right. >> That's right. So the the current state is from the likes of Bessie and several others as well as such where they're coming from a pick and place kind of background. So that means the businesses and and what they used to do well what they are doing very well is kind of doing the pick and place of the individual small chiplets right and they and the the placement arm the the mechanical arm with the stepper motor controls and things like that they are very good at doing the overlay right from the die onto the base wafer and then placing it down it doesn't use any force it just places it down onto the bond pads and then the the bonding step comes later when they do the anneal right So that is where the current technology and and state of the art is.
6:14 However, ASML is coming from a different location which is coming from the front end right. So that means ASNos tools they are regularly used in the subnometer alignment overlay right when you are trying to manufacture really intricate transistors your lithography patterning you're looking at extremely fine grain control right so it's easily a magnitude a higher precision right and so for ASML's perspective it's like okay if we already have this why not find a way to implement that for hyperbonding especially now hyperbonding is getting to finer and finer pitches right for your your bond from hybrid bond pitch right so how many signals can you get per square millmter down and in between the two dice is becoming more and more important and so by coming at it from a front end perspective they don't have any issues with regards to overlay right their challenge is how do we implement our capabilities or their capabilities into a system where you can bring the dice to the wafer or in this case the wafer to the d yeah so it's a pretty novel solution right and we also discuss some of the the challenges that they might versus the current technologies.
7:22 >> Yeah, let me take a step back. You guys mentioned this article at the beginning, right? This was >> February 2024. So coming up on 3 years ago and in the description, you know, of this article mentioning what exactly is hyperbonding talking through AMD 3D Vcash obviously now if I go back to the present day there's a claim in here that HBM will not adopt away for hyperbonding before 2029 if at all. Can you talk about like the implications of hybrid bonding where you think it's going to fit in maybe yeah the reasoning why >> yeah I would say the primary purpose of hybrid bonding is for logic right so because it allows you to sort of partition the IP all your different functional units into two separate layers and as you know like putting signal wires between these two units right to communicate between them is much shorter distance if you place them above each other right and you can have many more wires Whereas if you place them next to each other, you have some kind of limit on your data fabric, right? How quickly or how how efficiently one signal can talk to another. So actually I have an example right here. So this is the Huawei C2 phone and inside is the 9050 chip and it's the first chip to use first mobile phone to use hybrid bonding and two separate wafers, two layers, right? In order to split the IP and get the most out of the process technology that they have. Case in point again is for logic for power efficiency and for increasing the effective area budget in a limited size like a phone right so that is like the main use case we see so far whereas on the memory side right and the claims about hybrid bonding used for HBM those are primarily for packaging reasons means like how many layers of memory can I stack into a given maximum thickness right because all silicon has a maximum thickness of 7 775 micron right so slightly less than 1 mm and people want more and more capacity right so if I have hid bonded maybe I can have 50% higher gigabytes per HPM stack right on the on the best case scenario and so memory vendors have been you know putting a lot of R&D and a lot of marketing into hybrid bonding u but the ROI isn't there because fundamentally hybrid bonding is a much more expensive process to implement right versus traditional reflow or thermal compression bonding TCB which is what they are currently using for HPM right so there's a small benefit to thermal performance there's a small benefit to perhaps signals signal integrity however the main thing is just to get the density up and right now that is not the priority of most AI lads and most requests right we people are like like we have been asking and and the memory vendors have received a lot of requests to actually reduce the number of layers for given performance and bandwidth right so this is currently pushing bring back like the the the need for that many layers right and so if you don't have to use hybrid bonding then you shouldn't and that's why we also making that claim well it's not going to come anytime soon in any high volume for HPM and mostly will be for logic >> sure you agree with all that does that make sense >> yeah I think what how mentioned and also in fact we have written up a detailed article about the HBM like diseek or the so on that we have run through the economics about whether it makes sense to continue to stack more or for the time being use what we have right now the full high so I think if you read through that yeah you also get more color on why like right now or there's a delay about the HDN and on top of it I think just now we've mentioned about D wafer hyperbonding being more challenging in terms of the accuracy they need and the throughput So all these factors combined lead to the delay that we are we believe is will happen and that's why our timeline for the adoption will be 2029 or beyond.
11:25 >> Yeah, this is quite a big difference. It's not like all adoption of new tools in the fabs comes quickly or on time in in the past. But just looking at this ASML road map which was published in 2024 that you guys cite in the article there's a lot of hybrid hybrid hybrid hybrid hybrid across NAND and DRAM you know >> and of course ASML likes to you know it's in their best interest to to you know have an optimistic prediction of like the technology to the nation because you want to sell more tools you want extra complexity right they were famously I remember very famously u they had transistor density metric and a graph showing like a high NA adoption and the the density numbers were like totally off the walls right like 300 400 500 million transistors per square millm which is nowhere near what we even have even to this day so yeah we'll take those with a pinch of salt yeah >> makes sense okay so maybe we can dig into talking about the actual tool itself like what's super unique about it I can start by throwing the the patent diagram that you guys annotated back on screen maybe you can talk through a little bit of it.
12:35 >> well, I'll start but then I'll let Howie to continue because I think I still remember the day where we were looking at the graph and then how you were describing to us how the track like runs through and how and also there's an important part of the ecosystem change that needed that how he reviews. But what is really unique is that normally what we see or what we have on the market right now are chamber tools which means the tools they don't move and it's the dice that move to different stations and gets processed but if yeah as you pointed out here the unique thing about this tool is that well when we read the filings the padence and what SML drews is that it should be running on a track and they have B super track conveyance which is a company or a potential supplier for them to provide the track and then the fundamental difference as we pointed out is that for Bessie type of tool the D is prepared elsewhere and like the bunk head picks up the tool and then put them to the stations and for the final placement but in ASML's design it's that the dice seats on its own holder and then it leaves the carrier like it stays there move through different stations and also only leaves until till the bounding set and yeah I'll let how describe the other parts of the track and other tools that potentially could be interesting or could be challenging.
14:15 >> Yeah. So so again the super interesting part here is that you the D is not moving from the conveyor belt. So the dye is always staying on the conveyor belt and it's not moving right like however the dye comes onto the carrier when it's placed on the carrier it doesn't really matter too much because then you have the different subsequent stations that will kind of measure okay this is how the die is oriented on the carrier and then you'll make a subsequent compensation when you come to the bonding step later right but the main the main difference here is that each of the the two functionality each so-called chamber has to physically come down and approach the D right even down to the bonding step where the wafer has to come and approach the D that is on the carrier. So everything has to come to the the d the the d in question right the small little chiplets and so how do you design a system right where your let's say your normal metrology your measurement tools right now needs to be in a moving scenario right where it has to come down to to engage with the dial right and the conveyor system and so this is going to be pretty interesting to see how they're going to implement and because of the non-standard form factor right they will need at least you know some kind co-design agreements with several companies right who do like the pre the pre public phase in order for them to integrate their functionality into this track system right of course other matter is that ASMR could do everything themselves which they could right in terms of especially in the methology side it shouldn't have a problem but again right the challenge is how do you maintain the measurement accuracy when the tools itself starts moving moving to come and approach the D right so that's going to be a big a big question.
15:58 Another one is like how do you maintain cleanliness over such a huge surface area, right? Imagine your current tools, right? Although this is not like a front end transistor formation kind of clay, not to that level of cleanliness, but even so, right? How do you make sure that when the D moves from the to the different stations, this thread, we're talking about several meters, right? Several square meters of of area that you know can be exposed, right? So how they're going to contain it between when when the D moving between the tools and when the chamber comes down to approach the dive, how does it handle the environment like the air and the environment? That's going to be a very interesting question. Yeah.
16:36 >> Yeah. And the the critical thing you guys pointed out in the article is that a single particle between two wafers can unbond the area and result in a defective bond. So you specify alignment accuracy and then cleanliness. Can you distinguish the two of those and how they might both come into play and then maybe later we can talk about why ASML is set to benefit because they have a bit of experience keeping things clean so far.
17:05 >> Yeah. So the two major things right so alignment alignment is right you have to measure where the bond pads are relative to where you expected them to be and then make the relevant changes in terms of the positioning when you come down the wafer approaches the die. You want it to compensate for any kind of deviations not just in the XY position also rotational axis and even some stuff that is out of plane. So it means the D might be slightly tilted to one side to one angle. So so you know talking about six degrees of freedom in terms of how the D can be aligned. So again that comes under the purview of like having structures on the D that you can measure. So you know okay the D is in this specific orientation on the carrier on the on the conveyor belt and then on the wafer what is the between the describe lines of my of all the different dice on the wafer what is the position of that relative to like 3D space and so when you come combine when you when you bring the two dice together you have to make sure that they come vertically and they come align on the XY especially right so that is the main goal of alignment accuracy Right? So it's like the overlay and then you can approach down and contact the two the two surfaces together. Second one is on cleanlininess. So again because hybrid bonding requires extremely flat surfaces right and it has to be free of particles because the nature of the bonding is the oxide bonding from the dialectric right and then the anal later where it gets heated right and baked and then the copper expansion fills the the void fills the remaining gap. So if you have any kind of particles in between right not just affect that one bond that that is in the area but because silicon is it will lift up and cause a defect across the whole area. So it's almost like a you when you have some kind of impur right it's like forming a wedge where you know the whole surface cannot bond properly because there's something in the way. So you know making sure that when when it's clean at one station right by the time it arrives at mid station that you guarantee that it's still clean. That's a very important >> also. So these two as in the alignment the accuracy and cleanliness. They basically they determine the bonding yield which is very important because automatally when we use the tool we we want them to have good yield and then to be able to generate good throughput. So that's why these chat or the high requirements also make hybrid bonding almost a front-end process and that's why we are also seeing more and more front end tool makers. Now it's not just SML and because hyperbonding matters as in it's both globally but also matters more for China since now they are leveraging hyperbonding or advanced packaging to shrink the like shrink alternatively. So we're also seeing major Chinese semicaps they are moving to the hyperbonding or growing their advanced packaging tool capabilities like Nora Amech they have all made moves by acquiring or basically investing to build the tool capability.
20:24 >> Can you explain that a little bit more? What do you mean when you say that hyperbonding can take the place of shrinking logic note? Like you don't need high tools or EUV if you're here. How he's holding up the Huawei phone again. If you're going to build a phone like that, right, if you have hybrid bonding, you can still just make it perform better. >> Yeah. So, main thing is that they given their limitations on pro technology, right? What's what's available to them?
20:47 How do you maximize performance? How do you keep increasing performance performance per watt? And so, you know, very easy way to do that like is just to make the die bigger, right? Use more silicon, run it at a lower voltage, lower power. That's a very naive way to look at it, but it will help to increase your power efficiency if you have more silicon available for your use. And then hybrid bonding is like a better version of that because the two layers of silicon we are right next to each other right and you have a lot of wires connect to them. So because of the limitations that that they have in terms of what kind of process technology they can apply right so this hybrid bonding and this advanced packing is sort of like another avenue for them to continue scaling and that's why there's a lot of demand in China.
21:28 >> Okay. So maybe a little bit more on the technical side. Why why exactly do you think hybrid bonding allows them to improve performance per watt or performance per millimeter squared? >> Yep. So, a key example that Huawei has given and and we do see it in in this phone as well is that you're able to sort of split certain components, certain functional units within the core. for example, things that require high speed, right? You can actually place them closer together. And so there's less timing delays. There's less congestion required when these units communicate with each other, right? And why they're able to be put closer is because other non-critical stuff like let's say your SRAMM your memory cells, you place them on the bottom D, right? A different layer and so they out of the way and so the important stuff are closer together and then that allows them to for example improve the clock speed, right? They get a from now up to 2.7 GHz, right? So higher clock speed without increasing the voltage or the power right. So in but in a general sense right in a naive sense right just having more silicon more aerial budget for a given power envelope usually for and and also the same architecture usually it nets you slightly higher power efficiency right just because by running more silicon at a lower voltage right lower voltage means there's less leakage right so it means less power is being wasted to transmit the the signals from one end to the other right so this why haroning helps a lot in your sense >> makes sense okay and then Maybe Sure.
22:57 Can you explain a little bit about the implications on China that you're referring to there? Does this imply that a a hybrid bonding tool would not be subject to export controls or does it imply that you think it's within the scope of what a Chinese tool maker would be able to produce for themselves? So right now what we have seen as in we've also mentioned in the article is that Bessie is the leader in the D to wafer and then wafer to wafer we have more players like EBG SMPD and but still it's mostly the international incumbents that are dominant in this field for now but we are seeing that China or major Chinese semicaps are growing their capabilities and we believe it's the same as in for other tools as in there are geopolitical complexities that could drive the need or the motivation to grow the like as in the homemade tools. So that's why they are as in China is always motivated to build the like their own supply chain. So that is why we are seeing this more and more initiatives by Chinese tom makers to grow this.
24:11 >> Yeah. And you can see in the road maps as well right how aggressive they are in terms of implementing hybrid bonding in in like for example you just look at the data center side right they're working very hard to overcome the kind of power density limitations right so in order for them to to implement hybrid bonding and they want like a full you know they call logic folding this a full hybrid bonded design for the data center accelerators by 2030 right and we're talking about much higher densities compared to like TSMC's SYC bond page wise. So we're looking at you know for the kind of demand that they they want right especially given their process limitations right also looking at you know even like this currently two layers but even three layers right also by 2030 right that will you know reduce the yield further that just means you need more tools for the same yielded output right and so there's a lot of demand in those >> okay and something that you guys mentioned in passing in the article that caught my eye that I thought was interesting was the comments about the joint initiatives between ASML and TSMC, IFS and Samsung for moving from 6 in to 12in photo masks for high NA EUV tools.
25:22 Can you give me the high level and the implications there? Because that's also something that's not coming soon, let's say, but would allow for similar improvements, I guess, of being able to increase eye size and things like that. >> Yeah. So, so the main limitation of high is that your radical size is half, right? because of the way of the anamorphic lens that is squeezing the mass pattern squeezing it eight ways eight times in one dimension but only four times in another dimension. So you will end up having the D size of maximum of like around 400 square mm versus know currently is 850. So in order for designers to have like a full radical size right you either do a kind of a modified stitching right where you have a certain you know iMac talk about this ASMR talk about this where you have soal delineated in your floor plan in your chip design a specific region where okay I know there's going to be some kind of stitching here where I either use other layers to do the stitching other non high non high layers to do the stitching or I dedicate a certain specific to stage, right? So this is what's going to happen in the interim and then in 2020 time frame we're looking at this 6x12 mass. So that just means that the mass is now double the dimension, right?
26:39 Double the length in one dimension. And so when it squeezes eight times and four times in direction, you get back the full reticle, right? And so that, you know, eases a lot of the headaches and also the main thing is that it improves the throughput even more, right? So SMS is all about this high productivity tools. And so this is an extension of that where you get the full mask size but on the high end and so you know it frees up the design again right and then you can have higher throughput of the full radical >> and a little bit on the one is on the ecosystem side this also has implications for the entire ecosystem because it's not just SML that's changing or the mass makers but it's the entire supply chain so that's why we also need the time or actually for SML they also took time to to work with the fabs to initiate this because of the complexities for the supply chain and also just now a second point that how touched on is about the throughput and this is very important for SML because management also just mentioned in recent earnings call that their pricing is basically a value based pricing which means that as they increase the throughput the that's also driving up the pricing. So longer term that's also going to be beneficial for them.
28:01 >> Interesting. Makes sense. Can you dig in one layer deeper on what are the supply chain implications on some of this? Like maybe you guys cover it in the research and we shouldn't talk about it now and in that case excuse the question but maybe if that's not the case then high level like what technically is changing in the supply chain that you think would have implications. The main thing is the entire mask inspection, production, and some sort of like protection, right, with the pelicles. All of that needs to be updated to fit this larger 6x12, right? So, so the little fun side, right, it's not actually 12 in. It's like 11.2 in or something like that in order for the mask blank to fit in the current, let's say, like your hoops, your overhead material handling robots, right? So, but it's still enough to fit the the larger mass piping. So that's just one example. So like all your carriers, how do you carry the mass?
28:52 Then your pelicles, then if you have a double size mass area, then all your ebam metrology inspection mass repair, right? It's going to be even more complex, right? And so the whole industry needs to basically all agree on like, you know, how we going to approach this larger mass size. It's very akin to wafers going from 8 in to 12 in back in the early 2000s. Early 2000s. So yeah, we're looking at that kind of whole industry needs to move together to shift and that's why you need this kind of early commitment from all the foundaries and ASML to ensure that you know everyone is coming up to speed in the supply chain.
29:27 >> It does make me think that a little bit of what you were talking earlier where China could be more aggressive going for hybrid bonding and build an ecosystem around that could create even more of a split where ASML and the the foundaries that run their tools end up just pushing further on high and and make some decisions there. But then you mentioned that you get the retical size back and I'm I'm wondering if somehow they wrap around to the same thing for chip designers where designs that are used on one can now be actually more transferable to another stack of tools in some way. But I assume that's probably not the case. Anyway, give me your high level reaction to that. Do you think that there we we should expect with more expert controls and all the geopolitics at play that there's going to be effectively two separate tool stacks that you build a fab on going forward? there's going to be one side pushing on hybrid bonding and the other side pushing on larger photo masks and continue to shrink everything. So I already say that that is already happening on the EDA side of the chip design child right again because the way you design a chip with multiple layers and how you partition which block should go where right this is something that everyone else hasn't really had to deal with but China is pushing very hard on this so no Huawei has teamed up with several design companies to you know integrate like and and sort of like do the partitioning right for the different functional groups on everyone else's part right AMD is the original you know user of this SOC hybrid bonding right but their partitioning is a lot more simple right it's just looking at the L3 caches right SRAMM and then also the the so-called like the split line of the different layers it's very distinct right so the CPU calls go on this layer the memory goes on another layer right but whereas in the logic folding hybrid bonding case is looking at okay within the core I have all these little functions little for example like multipliers, tiling relays, buffers, you know, all the small little components that make up the core, those are being partitioned across the pool layers. And so this kind of very advanced design flow is already happening this split between the current western EDA tools that have never needed to do this in the first place and so they you know started doing their own. So I can only speak to the design side on and but on the supply chain manufacturing side no I'm sure Cherry can speak a bit more.
31:48 >> So in terms of the supply chain I think just now we've talked about there are multiple drivers for I think for China to be building their own supply chain or trying to accelerate as much as possible. So yeah, we're we're not an expert on predicting what the policies could be, but what we are seeing on the ground in China is that well, it's also from the companies themselves that they said that starting from this year, the domestic sufficiency initiative used to be state le. Now it's moving to the stage whereby it's more coordinated among the tool makers and also the fabs themselves as in they are working together to design to build the tools the semicap equipment or EDA and from ground level because what China needs could be different versus like rest of the world given some constraints that they have. So and we believe that that process and this kind of effort will not be affected with the policies as in export controls. In fact, if there are export controls, as we have seen in China's semicap localization rate in the past few years, the export controls could accelerate or push them or increase the motivation to to to work harder on that. So that's what we are seeing right now.
33:22 >> Makes sense, guys. Okay, I am roughly out of questions. Maybe the only thing that jumps to mind as being left is the question of what's left for ASML to prove as they go through this development of the hybrid bonding tool, but we know you you kept that behind the pay wall. So, we will skip it for now and say anybody interested in answering that question should subscribe to the research, check out the Wafer Fab equipment model and yeah, reach out and let us know if you have any comments about this. So, yeah, any final thoughts before we wrap up here, guys?
33:47 >> Yeah, just look forward to our tear down of this. Yeah, >> tear down of the Huawei phone. Let's go. We published some good stuff previously on both of those Intel and Huawei process which is awesome. Sure. Anything from you? >> I think it's always great to to be able to work with great colleagues like Howie and also Jordan yourself cuz every day I feel like the learning curve is 90° here. So I hope that our readers also enjoy the especially the technical part of our research and yeah we will do more and update you again on SML or other parts of the supply chain.
34:25 >> Awesome. Nice job guys. Thanks for joining today.