Ep. 019 - Inside the STEEL Lab: From Package to Transistor (Teardown Lab)

0:04 Hello everyone, welcome back to SemiAnalysis Weekly episode number 19. We are here with the Steel team. One of the coolest things, actually I would say definitely the coolest thing that SemiAnalysis is doing right now. The Steel teardown lab. We're going to dig into the public launch of Steel. That means an article where we did a teardown of some consumer chips and basically put on display everything that the Steel team has to offer. Joining me today we've got Andrew. How's it going, man? Welcome to the show.

0:35 >> Thanks for having me. >> And we've got Afzal. Welcome. >> Thank you. Hello. >> Awesome, guys. So I think a lot of the listeners are going to need some a basic intro, so hopefully you can bear with me as we go through this and explain some some things to the general audience. So let's let's start with this. Like Wags, can you tell me what's the Steel team and what is a teardown high-level? >> Yeah. so what is a teardown? I mean, it's literally what it sounds like, right? We take you know, in the case of our our first article consumer chip, we get take out of the package and we just start breaking it down and looking at what's there, right? We take it from the box we get it in all the way down to the transistor and everything in between.

1:19 You know, anyone listening understands data center, AI, consumer chips, everything's advancing at the speed of light, right? In some cases literally. and so there's a lot of competition within the marketplace. Who's in? Who's out? What are the advances? What are the the technical nuances of of every technology? Competitors are curious on how their competitors are, you know, within the same boundary conditions, how are they, you know, making decisions and how are they advancing their technology? And so a teardown goes into every aspect of that. Materials, process, integration, electrical engineering, architecture, design.

1:56 every kind of piece of that puzzle that we can look at, that's what we're spinning up this lab of steel, and that's what we're doing. And so, our first article that came out a few weeks ago is kind of the first taste of what's possible, what we're capable of. >> Awesome. Yeah, it was a great article, and we'll we'll definitely dig into it. So, want to get your take on this. When it comes to teardowns before Steel existed, obviously people would use the these outputs that Steel can produce in order to understand chips. Can you explain a little bit about the motivation of like what you use the output from the Steel lab to do in order to like understand chips?

2:35 >> Well, there's really two angles you can approach this from. One is from the chip designers themselves, and one is like as a competitor. So, example, if I am and I want to and I have the teardown of Nvidia GPU, I can see how they're using the area, how how much cash they're using, how much area is being used for the compute or for the memory or the IO. So, that's one major thing for them. And on the other side, for the chip designers themselves, they get to see what the process node is, for example, before they even start designing.

3:10 So, they can see this chip from Apple, then you can see this is what TSMC N3 looks like. This is what FinFlex looks like, and then we can this is our goal for when we actually make our own chips. >> Awesome. So, can you tell me a little more about exactly this article? Obviously, in the title talks about SMIC N+3 as well as Huawei's Kirin 9030. So, that's both the process technology and then the chip itself that you might be analyzing. Can you walk me through like a little bit of the high level of what you guys learned in the process of tearing down the chip?

3:45 >> First, let's go through some context. So, in 2021, they were SMIC started fabricating their own N+1 node, which was roughly equivalent to an 8 nanometer each node, but the one of the main problems it didn't have any SRAM. So, it couldn't be used for any big smartphone chips or even or AI accelerators. But now, then 2 years later, there is N + 2, which they use in a lot of their smartphone chips, and they're going to be using in their new Ascent G So, now we come to N + 3, which is their newest one that they just started using for smartphones. N + 3 is still shrink of the previous two generations, but the main thing is firstly the M0, which is the lowest metal layer, has shrunk a lot.

4:27 It went over about 15 plus percent. Then, you have the higher layers, which aren't so much, but on the the transistor level itself, there are so many major changes. And I guess one of the biggest things for our use case, I mean, for their use case, I guess, is that the SRAM is much smaller now. If it's even 10 percent smaller, 10 20 percent smaller, that is way better for any new chips you make, cuz over with some chips, maybe what, 2 percent is just SRAM. So, it's a very major component.

5:01 >> Awesome, yeah. Okay, Wacks, how how do you actually go about doing some of this stuff? Like, if you're going to try and figure this stuff out, maybe what's Can you walk us through the initial approach of like just sourcing the chip, and then where you go from there using all the incredible equipment and lab that you guys have built in Oregon? >> For sure. I mean, how do you get it? Consumer chips, that's easy, right? You you go to your neighborhood electronics dealer, you buy they're relatively accessible. When you do a teardown, you need a number of samples, right? You look at a lot of the stuff that goes on, you know, Twitter or wherever else, everything looks easy. You get a nice pretty picture, you get all these different details and analysis, but the amount of work that goes into that, the number of chips, the number of samples that you need to actually extract all of that, can be, you know, quite ridiculous. And so, that's what makes a lot of these consumer chips quite accessible, right? when we start getting into the data center and other places, as you said, acquiring these chips, accessing them at those price points, it becomes a very different thing.

5:59 it means, you know, we have to do a lot of planning. We don't just get the get these samples and and just kind of go crazy with them. We actually have to plan this out. It It means you have to understand the technology, you have to have expectations of what's there. I mean, this kind of feeds into other parts of semi-analysis, right? Whether it's VLSI or IEDM, and we we summarize all of these fantastic talks from all these, you know, manufacturers, foundries, design companies, right? We need to understand all of that, we need to understand what's going into a part, and that's just step one, right? So, we get this thing in our lab. We have a plan, we think we know what's there, we start unboxing it, we start, you know, in the case of a phone, pulling the screen off, looking at the chips inside.

6:35 It's all, you know, pretty, it's all fancy, but then we actually have to extract those samples. You know, everything is soldered together, everything is packaged. In the case of a smartphone, you have an SOC, right? And so, how is that SOC designed? Looking at a domestic chip versus, you know, different competitors and all the O-sets that are out there, how are these things evolving, what's inside? As we start looking at these, we can take a picture.

6:59 that's fine, but we actually have to break them down. We tear them down, we cut them up, we polish, we do all these things. It's very mechanical, it's very destructive, right? behind you and your screenshot is X-ray. X-ray's a non-destructive technique, just like going to, you know, the doctor. you look inside. It's not the best for you or the part, but it's, you know, what we would call non-destructive, and it gives us an idea, you know, at the micron scale. We always talk nanometers and and, you know, transistors, but at the micron and millimeter scale, there's a whole lot of detail and innovation there. Packaging is accelerating at a, you know, light-speed pace, you know, much faster relatively than the transistor technology is.

7:39 Not to say that there's not just as much work and probably more money going into it, but it's it's just just so much ahead in terms of complex packaging. Right? So, x-rays an example of these tools where we can start looking at what's inside, getting idea what's there. But then we have to break it up. If we cut it in half, you know, people love shiny die maps. There's so much you can understand from architecture cut architecture and design and scaling and and layout.

8:04 You know, those those things you can do, but once you have a die map, you can't cut it in half because you've already removed all the interesting stuff. And so we have a lab where we can do these delayering techniques. We can reveal the die map. We can reveal the floor plan. We can cross-section. We can cut. You know, these are all very mechanical, very hands-on things. You don't really think of that in high technology, but it's just like in the fab. You have CMP, chemical mechanical polish. You have wet etch. You have dry etch.

8:31 And then you have all these advanced analytical tools. We're looking at the most advanced technologies on the planet. And just like the people who develop those technologies need the most advanced tools. You know, a confident teardown lab needs those exact same tools because we're looking at things at the same scale and same complexity. And this is really why there's so few players in this space, right? It's it's an intensive thing and it's something that really, you know, shows the commitment of SemiAnalysis to steel to make this a very strong and value-add venture not only for SemiAnalysis, but you know, all of our clients and and anyone who can read our free material as well.

9:10 >> Awesome, yeah. Okay. Maybe we can walk through these things one at a time. So, the headline like first picture out of the lab is a die shot. Can you guys maybe just define what a die shot means and what it takes to get that first picture out of the lab. >> Yeah, let >> Awesome. >> I'll have you explain really what it means and then I'll I'll take over. >> Yeah, sounds good. >> So, what we have is the die shot and it's a full overview of the chip. So, you can see on every part die shot, you'll have certain structures, certain blocks. So, example, you have a CPU core, you have a GPU core, you have a NPU, you have your IO. All of these is your floor plan, your layout of the chip.

9:54 Then you can see that on a high level just with the just with the die shot. Yeah. You can see in the picture we have up there. All of the big blocks regions of the chip. >> Yeah, so what does it take to get a die shot and then to get the annotation of this done to the quality that you guys are able to do for this >> Andrew would he would answer this better. Yeah. >> Yeah, that this chip, this is the die, this is the silicon within the package.

10:26 It's within the phone. I we we have to just break that apart. but in a mobile device, this die is actually embedded inside an SOC a system on a chip. Right? And so, DRAM, memory, interposer, BGA solder bumps, and then finally the silicon is all sandwiched inside of there. And so, we very carefully through variety of heating and mechanical processes, desoldering, infrared heating, are able to extract the SOC from the phone. We're able to start removing all those die. We reveal just the piece of silicon, but the silicon isn't itself an entire stack of material. You have the transistor, you have the metal zero, the front end of line, the interpose the interconnects, you have the back end of the line all the way up to these very relatively large structures. And at that level, that's where you're actually contacting the chip. It's all the signal and the power and the routing.

11:17 But that really hides all that information that you showed. That that floor plan is all the way down at the transistor level. It's where all of the SRAM and memory and logic and all those different functional units are there. And so, we actually have to work our way through all the metal layers. We have to get through all the back end, all the interconnect down to the we call the poly. That's a bit of a misnomer these days. There's no more poly in these in these devices. It hails back to when planar transistors use polysilicon for their gates. You know, these days are tungsten tin nitride these other materials. But by actually removing through chemical mechanical processes all the way down to that silicon, we can actually extract a whole lot of information even at that nano scale using optical imaging. And that's what you see here, these very high res resolution optical images that we can then extract a lot of information about, you know, different functional blocks and architectural decisions.

12:09 And that's really where, you know, we we put a lot of labor into the lab to extract these. And we hand that data off to, you know, the experts in architecture and design and silicon layout who can analyze all of the kind of history and progress and optimizations that all of these different design houses do put into the fab and and, you know, put into a final product. >> Quick sense. Okay. You're kind of introducing another term and obviously like a die shot has annotation, but maybe you guys could explain a little bit about how the floor plan of this chip, I guess, and and the analysis can impact somebody's understanding of how a chip works. So, before actually getting a die shot, getting it annotated, maybe have a certain understanding of how one of these SOCs works. And then after getting it done, you have a different understanding, a deeper understanding of it. So, is there something that maybe you guys learned about this particular SOC or is there like a more generic point that you can make to explain why somebody would use a floor plan like this to actually or sorry, a die shot like this to actually inform what more analysis you would want to do on a given chip?

13:20 >> For this for this example here, the CPU and the GPU were relatively well understood because when you do your benchmarks, when you do your reviews, even when the company announces it, they'll usually be quite clear on what how the CPU works, how well the GPU works. But one thing we noticed was the NPU. So in the previous generation, the 9020, it was only it was one slightly bigger core called a light core and a one tiny core.

13:48 But in the new one, now it's a one light core and two tiny cores. So this was something that we really didn't know before because nobody knew how to benchmark NPU frankly. And like no and Huawei hasn't said anything about their own NPU inside the Kirin SoC. >> Yeah, so on screen on the left we've got the 9020 and on the what on the right is the 9030. and so you guys view this as like a I don't know, a public contribution to the public's understanding of how this chip works, right? Like this is just us giving away some free information that we're able to understand based on the work that's done in the lab.

14:30 >> Yeah, definitely. Yeah. This is definitely something that wasn't known before and you're just giving it to public. It's not it's not super private. I know that chip can't in theory get it out so there are some some people or especially the Chinese in China that will take the buy the chips themselves and then do their own do their own die maps. >> I think this is an opportunity, right? For for steel, for semi analysis, a lot of these consumer devices, people are very interested in them. They're they're a very different technology that might go into a data center AI where you know, we as a company also have a lot of interest. And so this is an opportunity for us to you know, both demonstrate what we're capable of, you know, reveal some you know, quality information that's of value to to our clients and our readers and and just put it out there, you know, give us a taste of of kind of, you know, what's behind the wall that we that we're looking at in in the you know, the more kind of data center and AI space. And so, you know, that's an area too where we welcome, you know, any ideas, anything that's interesting.

15:35 You know, bring bring it forward. we're we're up to the challenge. >> Okay, so I'm I'm really interested in the what you learned about the SMIC process as well here. Going to skip packaging and memory comments on the chip for now unless you guys have comments and and dig into the process. High level to start this section, what what's the takeaway, I guess, in terms of an understanding of the SMIC N+3 process that you guys got from this analysis?

16:08 >> I thought I I mean, I think all of this is just taking a step back and looking at the big picture things, right? It's it's a very interesting case study. you know, advanced leading edge has moved on with EUV and there's certain geopolitical reasons why SMIC is is not able to use that. And so, when one hand is tied behind your back, you figure out a way to innovate, right? you adapt. And this is absolutely an area where, you know, these restrictions have forced innovation, have forced progress, and compromises that other fabs and other foundries may may not have had to make.

16:43 you know, there almost is a is an analog back to Intel 10 nanometer here where they chose not to go with the EUV, right? And these types of same scaling challenges were present. And they had to innovate as well and everyone saw the performance and yield and challenges and delays that went on there. But here we are with you know, SMIC N+3 with an extremely aggressive scaling using DUV at the M0 layer and and above. And you know, that I don't know if you have any of the the pictures up, but we can look at that process. We can see where they're reaching parity with the world's leading fabs. We can see where they're making those compromises.

17:18 you know, the the metal zero, the the different layers and etch stops and barrier layers and you know, the different metals like are are very very clean. but you know, there's there's other aspects of this where we see as well like with their their final etch stop and and their seed layer where and the taper of the profiles of the these metal layers where they they clearly made some process decisions to to manage yield and and performance.

17:46 that you know, with the right patterning, they might not have had to, but they found a way, right? They they sell these in the market. >> Okay. Okay, so what's the maybe next layer down in terms of the process? Like of course, there's I'm I'm thinking in terms of how you guys do the analysis when it comes to a teardown. So you got a die shot and then you start moving on to other things, particularly the TM cross-section. Maybe you can talk a little bit about that and some of the tools that you guys use in order to actually do this analysis.

18:22 >> Absolutely. So I mean, we're we're really looking at the silicon at this point, right? Using TEM. The things are aggressively scaled down to the nanometer level. There's a variety of tools that that we can use here. Again, we use mechanical polish, you know, something that seems very kind of rudimentary, but with the right technique and right experience, you can actually reveal a lot of tiny structures, a lot of tiny detail. but going a step beyond that, we use a a tool called a FIB, a focused ion beam tool that actually uses gallium ions.

18:50 You focus it into a tiny beam and you can scan it across a sample and actually sputter or ablate the material away. And so when we have a floor plan, we know that there's different structures that are using different types of transistors or routing, we can actually use this tool to go and dig in and create these cross-sections. those cross-sections can be imaged in a SEM or a scanning electron microscope. A SEM is perfectly capable of looking at things at the nanometer scale all the way up to the millimeter scale. But, when you're getting down to the front end, when you want to look at a transistor itself, when you want to look at your gate metals and and all of your contacts and your interconnects, you need to go to a tool called a TEM or a transmission electron microscope. And so, much like an SEM, you use a scanning or parallel beam of electrons. You accelerate these things to crazy high energies that makes them have very short wavelengths, which allows you to resolve these tiny tiny structures. But, the crazy thing about TEM is that you actually you can't just image a face.

19:46 You can't just look at something like you would, you know, with your human eye. You actually have to make these things so incredibly thin you know, hundreds of nat- Sorry, hundreds of atoms thick in order to actually look through it with these electrons. The electrons pass through it, they interact with it, and on the other side you can collect an image. And that's exactly what you see in the e- these TEM images that allow us to look at the fins, look at the interfacial oxides and gate metals and contacts and interconnects.

20:14 Right? And so, this is where we can extract, you know, the tiny little functional units, the different types of cells, you know, and the way the circuits go together, but also how do you contact things? How do you route things? How do you What different metals and materials, conductors, right? Semiconductors, it's a whole world in the periodic table that that goes into these things, a whole world of processes, very complex processes. You know, thousands of steps that go into make, you know, these devices, you know, billions of transistors in a phone across millions of phones, you know, there's just so much detail and nuance that, you know, we go into the the tiny little, you know, under the microscope and look very very locally to try and and see how it's done.

20:59 Okay, I want to pick one thing out. I I found a few of these images really interesting when reading the article and trying to understand a lot of stuff. if we look at something like cell height, which is on screen right now, and comments on the reduction from N + 2 to N + 3 in cell height, can you talk about what that means in a in a chip? I I think a lot of people maybe have a a high-level understanding that like, you know, 7 nm more than 5 nm more than 3 nm, but they don't necessarily understand how this actually applies to something specific like cell height. Can you talk through a little bit of of that and what the result when you realize this at the end and you have these images, you can you can actually, you know, draw in terms of how people are using this process technology.

22:00 >> Yeah, so the main thing that two main things that you can still transition shrinking. First is your cell height. So, and this Yeah, it's first is your cell height, which is how which determines how many fins you have, how many metals you have between them. Then you also have the gate pitch, which is what actually contacts the silicon channel that contains that all your transistors that all your electrons go through. So, when you have these two, you have a rectangle shape, a grid shape, that you can start laying out across the entire chip. Within that layout, you can have a maximum of one P-MOS transistor and one N-MOS transistor. So, if you just keep Well, that is your basic transistor density.

22:43 Then on top of that, you have all the DTCO boosters, which maybe I'll explain later, but all of those DTCO boosters will add more to the density. So, that's on the on the highest level. But then when you go down, when you shrink your metal lines, your resistance will go up because it's smaller, obviously, and also because the liner needs to become thicker relatively. So, if you had a 20 nm 20 by 20, you're checking it to the 10 nm, now your liner is twice as much of relatively.

23:16 So, that will add a lot of resistance and you'll add capacitance. So, all those reduce the performance of the chip. All the modern fabs all of the leading edge fabs have found whatever whatever techniques to improve that and to make it not so much a problem. That's how even on your 5 nm node from TSMC, AMD can still clock to more than 5 GHz. Intel on their 7 on their Intel 7 node managed to clock more than 5 GHz, almost 6 GHz even.

23:47 So, all those factors for the the resistance, the capacitance, all the parasitics, all of those will affect the final final chip. >> Maybe you could talk a little bit about the concept of a library here. So, when you're obviously you're trying to reduce the density across or improve density across different process nodes and we can see that improvement as you go from n + 2 to n + 3 in these examples that, you know, are in the article. But, there's different ways in which people can actually design a chip to use this stuff. So, maybe you can explain the concept of a library and then what you guys realized in terms of what libraries are being used in the Kirin 9030 that was torn down.

24:32 >> So, essentially a library is a group of all the of all the basic cells that the designer wanted to use, like an AND gate or a or even up to a adder or some small block that'll be just integrated into a CPU, a GPU, or anything else even. So, all these small blocks, they have the dimensions like the cell height, the gate pitch, all of those. Example, if Example an inverter might take up two cell heights and one gate pitch for example.

25:03 So that is your dimensions for that one cell. So if you just keep expanding and then this library you have different options. So one will have this cell height, one will have maybe have 50% more cell height, but you can have more fins so you can have have more performance basically. Then on the other hand you might want to go down in fins or gate pitch then you have a different library. So this library is just a set of all the cells you can be using as a designer.

25:32 So on N7 for example, there was two primary libraries. There was the high density one and the high performance one. So this also carried over to N6. The high density one was used by most people like Apple, AMD, they all used the high density. But on the other hand for high performance was used on a few Qualcomm CPUs for the most high performance CPU cores like the big cores, the prime cores. And then even after that there was another specialized library for Nvidia for their A100 GPU.

26:03 They used a HPC library which was while the high density was two fins, the high performance was three fins. The HPC library was four fins even. So there is a huge amount of current they can pass through. You can have a much higher performance for your GPU for example. >> Can you comment on the impact that export restrictions have had or really just the fact that Huawei has got to use SMIC what that has what sort of impact that has on the chip designer and their use of libraries?

26:39 >> The main thing here is that Huawei was one of the best chip designers before the ban. They were the ones developing on TSMC N5 at about the same time as Apple. Which if you know Apple's relationship with TSMC it means a lot, really. So, when they had to transition to the speak notes instead, which are much worse, to be honest. So, they had to adjust and they have to make the make use of every single transistor to the best of their ability. It all comes down to for them at least it came down to architectural improvements. That's how the 9020 is better than their old 9020 9030. Those are better than their older 9000 that was on TSMC N5.

27:17 So, when the the chip designers really had to focus on transistor efficiency. >> Is there a time for you to also talk about DTCO cuz it it has a role here as well, right? On any given process, on any given node. >> Yeah, it does, but I didn't really mention it cuz N+2 and N+3 are about the same for DTCO. Yeah. >> Good point, anyway. What what jumps to mind when you hear this sort of discussion about libraries and and stuff like are you thinking about I don't know. What you what jumps up what jumps to mind?

27:54 >> What jumps to mind to me is what's next in terms of the technology, right? I I'm very much a manufacturing guy. I love the complexity of scaling. There's two aspects of that. One, right? Transistors are scaling, they're reaching certain limits and we're we're having to innovate in different ways. Backside power is already here. Gate all around has already been here. For a teardown lab, those represent new challenges. They require new types of processing. That's something you see with 18A. Even with floor plans, you see that the quality of the floor plans and die maps on these technologies are much much harder to achieve and that actually kind of you know, there's all sorts of collaterals, not just in the design and development of these technologies, but in terms of the failure analysis, the fault isolation, the debug, right? All the all of these other kind of areas also have to evolve and advance in terms of technology and capability and and innovation. And so, that's the area that I live, that's where I find the things very interesting. And then at the other extreme is, you know, packaging.

28:54 You know, the this mobile SOC is not the most interesting package, but there's still some interesting innovations there. We'll be coming out with a few more articles looking at more complex packages here very shortly. Right? But it's the same thing. Things are scaling to sub-micron for, you know, hybrid bonding and and these other aspects. And it's again, it's pushing into these areas that are incredibly hard to manufacture. They're incredibly hard to analyze. And so for a teardown lab, that's a lot of fun. It's a new challenge. Right? Just how do you collect and analyze and and see this information? But then, you know, you you hand it off to the designers and the experts in that space and they're finding totally new things themselves.

29:35 Right? >> Can you explain a little more on on the challenge? Like what what makes it more challenging to teardown for you guys? Like what's what's the roadmap for you guys? >> So backside power is an interesting one. Right? You have your top metals, you've always had your signal and routing above, but things are getting too crowded and there's all these different signals and these different things that crosstalk and have capacitance, right? And so it motivates trying to use the other side of of the device to to route power or signal, separate those things, let them relax. Right? Our the title of this article, you know, it was it was kind of a joke, right? It wasn't meant to be serious. And it it really has to do with the backside power. Which allowed Intel's signal to to relax in terms of scale. But what that means is a lot of the work that we do for sample prep, say for delayering, you might come from the top and remove all those metal layers and you can just land on the transistor.

30:29 Right? It's it's a relatively of all the challenging things there are to do, it's a relatively simple thing to do. But now all of a sudden you don't have all of the silicon underneath. You don't have finfets, you have gate all around. If you take those same approaches, everything just kind of falls apart. And so, you have to do things, you have to approach things differently. You have to develop new processes. And so, all all the teardown labs, anyone trying to take these approaches there are having to figure that out.

30:55 and you you really saw why it took a little longer for everyone to come out with those capabilities. Gate around all around itself is a is a new challenge, right? Every channel, you have the whatever you call it, the MCB or ribbon fed or gate all around. You have all these channels of silicon on top surrounded by gate. but they're effectively floating in in the sense that you have these different material systems. And so, if you're etching, if you're processing things, you deal with the chemistry, you deal with these different materials and layers to try and reveal them or remove them. And all all the sudden, everything's not just anchored to hundreds of microns of silicon, it's just kind of sitting there in some metal. And so, that creates new challenges in and of itself for sample prep.

31:38 Packaging again is really cool. we have these different imaging modalities. Optical imaging is limited to, you know, around a micron or bigger, but you only see what's on top, what's transparent or or what reflects. Scanning electron microscopy TEM can go down to the nanometer scale, can go down to the atomic scale, but it takes so much work to look at things and you're very limited in how much you can see. In between, you might have x-ray, but x-ray really struggles under a micron. And so, now that packaging, hybrid bonding, interconnects, all these things are scaling into this almost no man's land of technology and capability, so how do you see the things that are in between what these different analytical modalities can do? and how do you approach that and how do you make sure not only as an R&D lab, how do you actually make the stuff mature and and excel, you know, make it a high volume process, but then for a teardown lab like ourselves, how do we get in there and derive all of the information that that, you know, creates competitive advantage for our client.

32:43 >> Exciting, man. Also, on the other side, let's say you guys have done some teardowns, you know what's coming, but what's most exciting for you? Is it the consumer stuff, the data center AI stuff, CPUs, GPUs, switches? What What are you excited that's coming? >> Generally, it's the data center. All of the data center GPUs with the huge packages. With example, now cores is up to 5.5 vertical going even larger.

33:14 It is coming out in some new GPUs. So, all that is very interesting on the packaging side. But, the one one more interesting thing, but this one is on client side instead. Cuz Huawei recently announced their logic folding, which basically you have your two chips, but you stack them together and you treat them as a single chip because of the very very small very very small pitch hybrid bonds, which are for the first generation super 1.5 micron.

33:41 Which currently AMD, for example, is only using 6 micron in their V-cache and their MI 300 series. So, when you shrink it so much, it's effectively able to act like a single big circuit. So, you can join blocks on one layer with another layer and it's relatively efficient. Well, that's what they're claiming at least. So, when we were Hopefully, we'll get it later this year and then we can tear it down and see all of the amazing innovations that Huawei is doing in that regard.

34:10 It's basically their approach to avoiding the DUV scaling even further. And plus three is already quite difficult. So, if you had to go even further, then it maybe you'd hurt a lot for yields and for cost. Yeah, that's what >> Excellent, guys. Okay, anything that you think has been left unsaid in this overview. Try to cover everything that Steels up to everything that people can expect to see and a little bit of a high-level tour of the article, which everybody should go read. If you're interested in everything we've talked about, please go check out that article and stay tuned for new stuff. But Yeah, what Is there anything you think has been left unsaid so far?

34:53 >> Number one, this is just the beginning. we're excited to share more content right there on the front page. we've got a lot going We're cooking in the background as well. so if you're interested, if you think there there's something some unmet need, we're very up to the challenge. We want to answer those unmet needs. we want to solve those problems that aren't being solved elsewhere. Answer those questions you might have. So yeah, we're excited. We're hiring. We're growing.

35:20 You know, but reach out. >> Yeah, it's a big team already, but definitely growing. Also, how about you? >> I would just see have a look out for all of our amazing stuff coming out soon. We have a lot of consumer chips coming out and we'll be glad to share about our what we find on all of them. All of the most leading-edge stuff, some of the most interesting advanced packaging, and it'll be very good to for everyone to see it.

35:46 >> Awesome, guys. Well, congrats on the launch. Excited to see more and thanks for stopping by and sharing a little bit this week. nice show. >> Thanks, Sharan. >> Thanks everybody for listening and yeah, take care. See you on the next one.